Technology scaling allows a great number of system components on a single chip. From 65 nm and below, computational and network chips include multiple cores requiring a large amount of memory per chip. Static random access memory (“SRAM”) is often the first choice, given the need for high-speed random access. However, increasing leakage power per transistor makes SRAM less attractive as on-chip memory densities grow. Also, process fluctuations affect SRAM cell stability and decrease static noise margin especially at low voltage. In large power sensitive designs with embedded memory, system designers are turning to embedded DRAM because it is denser, has less power consumption in standby mode, and can have better low-voltage operation.